1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a method for controlling the nonvolatile semiconductor memory device. For example, the present invention relates to a NAND flash memory and a method for controlling the NAND flash memory.
2. Background Art
In recent years, NAND flash memories are widely used as large-capacity nonvolatile memories, especially for portable information terminals. One of the techniques for erasing data from a NAND flash memory involves withdrawing electrons from the floating gates of the cell transistors serving as memory cells toward the cell well side (the area in which the cell transistors are formed). More specifically, data erasing is performed by applying an erase voltage to the cell well and a predetermined voltage to all the word lines in a selected block (Japanese Patent Laid-Open No. 2005-116102).
After the data erasing operation is performed, an erase verifying operation is performed to confirm that the threshold voltages of all the cell transistors having the erase voltage applied thereto are equal to or smaller than the upper limit of the allowed threshold voltage range.
In this erase verifying operation, however, the lower limit of the threshold voltages is not controlled, and therefore, the threshold voltage distribution widens in the negative direction. The widening of the threshold voltage distribution is not preferable, leading to incorrect data writing and threshold voltage variations.
One of the conventional methods for narrowing a widened threshold voltage distribution is the method by which data rewriting called “soft write” (or “weak write”) is performed after data erasing (Japanese Patent Laid-Open No. 2007-305204).